IBM has revealed a prototype chip featuring approximately 100 billion transistors on an area the size of a fingernail. This architecture, called nanostack, vertically stacks transistors in two layers on a silicon chip, doubling the density compared to the company's previous state-of-the-art technology announced in 2021. The leap could extend Moore's Law for at least another decade, researchers say.
For more than half a century, chipmakers have followed Moore's Law by cramming more transistors onto a chip through shrinking their size. But in the last 15 years, transistors have reached dimensions of just a few dozen nanometers, where quantum mechanics starts interfering with their function. They cannot be made smaller. The solution, engineers explain, is to build upward.
IBM's new chip stacks transistors in two layers, a technique known as complementary field-effect transistor (CFET). Compared with the previous architecture, chips built with this approach can perform up to 50% more work in the same time and improve energy efficiency by up to 70%. Jay Gambetta, director of IBM Research, called the step a "meaningful leap forward" during a press conference. Dan Hutcheson, vice chair of TechInsights, added: "Absolutely, it's transformational. This puts another 10, 15 years on the roadmap."
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The layered structure of the nanostack chip
To build the chip, engineers first fabricated transistors on a silicon layer, then placed a second silicon layer on top and fabricated another transistor layer directly above, creating electrical connections between the two levels. Unlike competing approaches such as AMD's 3D V-Cache, the transistors in the second layer are not aligned directly above the first layer's transistors but are staggered. This simplifies wiring and offers other advantages. Each transistor channel consists of three nanosheets each 15 atoms thick, spaced 9 nanometers apart.
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IBM has dubbed its technology "sub-1 nanometer" or "0.7 nanometer," following a marketing convention that does not correspond to a physical dimension but indicates generational progress. The actual distance between transistors remains around 40 nanometers.
Manufacturing challenges and future prospects
Producing multi-layer chips poses thermal and yield challenges. Building a second layer without melting the connections below requires low-temperature processes: IBM succeeded in keeping manufacturing below 400 °C without revealing details. The failure rate is higher for multi-layer chips, as a defect in one layer compromises the entire chip. However, IBM expects that within a decade, nanostack chips will be widely used in data centers, helping manage energy consumption.
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The new design offers a general way to arrange transistors, and IBM will partner with semiconductor manufacturers to produce actual chips, including GPUs and CPUs. "I expect to have many conversations with designers about how they can use this technology," said Huiming Bu, IBM's vice president of global semiconductor R&D. The chip builds on nanosheet technology already used in the most advanced transistors since 2022. The approach parallels efforts by Intel, Samsung, and TSMC, but IBM's staggered stacking sets it apart.
For more on industry trends, read about Apple's price hikes on Mac models due to memory costs and Microsoft's upcoming Xbox price increases. For broader context on chip evolution, see the Wikipedia page on Moore's Law.
Source: https://www.technologyreview.com/2026/06/25/1139696/ibm-unveils-sub1nm-chip
